Metaharmos AMBA Interconnect IP delivers high-performance, standards-compliant solutions based on ARM’s Advanced Microcontroller Bus Architecture (AMBA) family — including APB, AHB, AXI, ACE, and CHI protocols. These interconnects form the backbone of System-on-Chip (SoC) communication, enabling efficient data exchange between processors, memories, and peripherals with optimized bandwidth, latency, and power characteristics.
Our AMBA-based IP portfolio is designed for seamless integration into complex SoC architectures, offering configurable performance levels for both low-power embedded systems and high-performance multi-core processors. With proven verification, flexible topology options, and full compliance with ARM specifications, Metaharmos provides scalable interconnect solutions that accelerate SoC development and ensure interoperability across diverse design ecosystems.
APB (Advanced Peripheral Bus)
APB provides a simple, low-bandwidth interface optimized for connecting low-power peripheral devices such as timers, UARTs, GPIOs, and control registers.
- Key Features:
- Low complexity and minimal power consumption.
- Single transfer, non-pipelined communication.
- Suitable for peripheral and register access.
- Use Cases: Ideal for microcontrollers and low-speed peripheral subsystems.
AHB (Advanced High-performance Bus)
AHB offers a high-performance, pipelined bus architecture suitable for connecting CPUs, memory, and DMA controllers. It balances performance and complexity, making it ideal for mid-tier SoCs.
- Key Features:
- 32-/64-bit data bus with burst transfers and split transactions.
- Single master or multi-layer interconnect support.
- High throughput with minimal arbitration overhead.
- Use Cases: Suited for microprocessor cores, memory subsystems, and real-time applications.
AXI (Advanced eXtensible Interface)
AXI is the most widely adopted AMBA interface for high-performance, high-frequency designs. It supports out-of-order, multi-threaded, and parallel transactions, offering exceptional scalability for modern SoCs.
- Key Features:
- Separate read/write channels with independent handshakes.
- Support for multiple outstanding transactions and burst transfers.
- Low latency and high throughput for multi-core processing.
- Use Cases: Commonly used in application processors, AI accelerators, and high-speed data paths.
ACE (AXI Coherency Extensions)
ACE extends the AXI protocol to support hardware cache coherency across multiple processing cores. It enables multi-core and heterogeneous system architectures to maintain coherent memory views without software overhead.
- Key Features:
- Full support for coherent cache operations.
- Integration with ARM’s coherent interconnect and cache hierarchy.
- Snoop and shareable transaction management.
- Use Cases: Ideal for multi-core CPUs, GPU-CPU systems, and heterogeneous SoCs requiring coherent data sharing.
CHI (Coherent Hub Interface)
CHI represents the latest evolution of the AMBA interconnect architecture, offering scalable, high-bandwidth, and fully coherent communication for next-generation multi-core and multi-cluster systems. Designed for server-class, AI, and HPC applications, CHI provides advanced features to maximize system efficiency and scalability.
- Key Features:
- Packet-based, layered protocol for scalable interconnect fabrics.
- Support for cache coherency across multiple clusters and dies.
- High throughput, low latency, and quality-of-service (QoS) control.
- Compatible with ARMv8 and ARMv9 architecture-based systems.
- Use Cases: Optimized for datacenter SoCs, chiplet-based processors, and AI/HPC architectures.